Akash Kumar Gupta

ADDRESS: Room No.-314, Indian Institute of Technology, Hyderabad

Email id- ee12m1004@iith.ac.in

Contact No. +91-7842662472

Career Objective

To succeed in an environment of growth and excellence, to work with commitment and sincerity

for the whole some benefit and wellbeing of the organization.

Profile

Successfully Taped-out Chip for micro scale energy harvesting in UMC 180 nm

technology

CADENCE DESIGN CONTEST 2014 All India Winners in the Master's category

Sound knowledge of Analog/Digital IC Circuit Design, Device physics and Memory

Design

Designed charge pump based DC-DC converter and voltage doubler based startup circuit.

Designed Power Management Block for energy harvesting unit

Designed low power Comparator, POR and BGR circuit

Hands on experience in Layout Design in UMC 180 nm technology

Familiar with CAD tools, programing language

Possess strong interpersonal, organizational, self-management skills

Education

July 2012-June 2015 Master of Technology in Electrical Engineering (Microelectronics

and VLSI), Indian Institute of Technology Hyderabad % / CGPA-- 8.67

July 2007-June 2011 Bachelor of Technology in Electronic and Communication

Engineering, Meerut Institute of Engineering and Technology

% / CGPA-- 72.14

2012-- Gate Percentile

98.73

Software Skills

Programming Languages: C, Data structure, Verilog HDL, Assembly Programming (8085,

8086), MATLAB

Tools: Circuit Simulator CADENCE virtuoso, Layout Design with DRC, LVS and PEX using

Calibre with Cadence Virtuoso interface, Modelsim, Xilinx ISE, SILVACO TCAD (Process and

Device)

Projects

M.Tech. Thesis: Charge Pump based Ultra Low Power Micro Scale Energy Harvesting System

for Low Power Application

Supervisor: Dr. Asudeb Dutta, Assistant Professor, EE, IIT Hyderabad.

Description: Energy harvesting from natural ambient like solar, thermal and vibrational

transducer has emerged as a promising solution to tackle power supply challenges in

miniaturized devices such as wireless sensor node, biomedical implants etc. We aim to design a

fully on chip energy harvesting system for wearable and portable devices using charge pump,

thus eliminating the need for off chip inductor. In this work, energy is scavenged from single

transducer (solar/thermal) at very low voltage (150-450 mV). The system involves a simple feed

forward MPPT unit, battery management and power management unit along with an independent

cold start up circuit to trigger system from zero charge condition.

Contributions

Design of charge pump based DC-DC converter for energy harvesting from solar and

thermal transducers.

Design of sensor circuit to detect the environmental conditions, so as to turn on and turn

off the power converter element for power saving.

Design of battery management unit to protect battery from under voltage as well as over

voltage. Also, it facilitates to turn on startup circuit when battery voltage drains out.

This design has been successfully Taped out in UMC 180 nm technology. Cadence

Virtuoso has been used as the tool for entire design flow. The GDSII has been sent to the

EUROPRACTICE IC Services offered by IMEC for fabrication.

Software Used Cadence Virtuoso, Analog Design Environment 180nm technology

Course Projects

Power efficient reconfigurable charge pump for micro scale energy harvesting.

A charge pump with high voltage step up ratio is essential to boost the voltage from tiny

transducer as well as to charge an energy buffer for storage. Conventional Linear and

Fibonacci charge pumps have better current deriving capabilities at higher and lower

voltage ranges, respectively. So we design reconfigurable charge pump topology which

can utilize merits of both Linear and Fibonacci charge pumps for wide range of input

voltage.

Low complexity algorithm for linear system solver

This project mainly aims at exploring the symmetry potential of determinant computation

based on the conventional approach of cofactor expansion of determinant calculation.

SRAM Memory Design

256x64 SRAM cell design using 65nm technology considering the parasitic effect of

wires using RC delay modeling in Cadence Virtuoso to analyze timing for read and write

operation of critical path.

Relevant Courses

VLSI Technology, Analog IC Design, Digital IC Design and verification, Embedded Memory

Design, Advanced Digital circuit Design, Embedded Design Systems, Semiconductor Device

and Modeling, Digital signal processing

Publication

Gupta, A.K., Joshi, A., Gajare, V., Ghanshyam, H.S. Dutta, A. “Power efficient

reconfigurable charge pump for micro scale energy harvesting”, Microelectronics and

Electronics (Prime Asia), 2013 IEEE Asia Pacific Conference on Postgraduate Research

Achievements

CADENCE DESIGN CONTEST 2014 All India Winners in the Master's category for the

project title "Inductor Less Reconfigurable Charge Pump Based Micro Scale Energy

Harvesting"

Winner of Quiz Competition conducted by VEDAIIT on “Microelectronics & Analog

Mixed signal Design” with Quiz Master Sam George, Director of Global Foundries.

Runner up for Intra IIT carom tournament 2013

3rd

prize for ROBOTICS in Kolaahal-09 (College Technical Festival)

2nd

prize in Skit competition held at B.B.D.I.T (Ghaziabad)

Participated in Robo Olympiad in Incord-2009 (the annual technical fest of HBTI )

Hobbies

Playing (Badminton, cricket), running, swimming, gym, watching movies,

socializing with friends

I hereby declare that the information furnished above is true to the best of my knowledge.

Akash Kumar Gupta