datasheet icl7135

7/27/2019 DATASHEET ICL7135

1/145-5

August 1997

ICL713541/2Digit,

BCD Output, A/D Converter

Features

Accuracy Guaranteed to1 Count Over Entire20000Counts (2.0000V Full Scale)

Guaranteed Zero Reading for 0V Input

1pA Typical Input Leakage Current

True Differential Input

True Polarity at Zero Count for Precise Null Detection

Single Reference Voltage Required

Overrange and Underrange Signals Available for

Auto-Range Capability

All Outputs TTL Compatible

Blinking Outputs Gives Visual Indication of Overrange

Six Auxiliary Inputs/Outputs are Available for Interfacing

to UARTs, Microprocessors, or Other Circuitry

Multiplexed BCD Outputs

Description

The Intersil ICL7135 precision A/D converter, with its multi-plexed BCD output and digit drivers, combines dual-slopeconversion reliability with1 in 20,000 count accuracy and isideally suited for the visual display DVM/DPM market. The2.0000V full scale capability, auto-zero, and auto-polarity arecombined with true ratiometric operation, almost ideal differ-ential linearity and true differential input. All necessary activedevices are contained on a single CMOS lC, with the excep-tion of display drivers, reference, and a clock.

The ICL7135 brings together an unprecedented combinationof high accuracy, versatility, and true economy. It featuresauto-zero to less than 10V, zero drift of less than 1V/oC,input bias current of 10pA (Max), and rollover error of less

than one count. The versatility of multiplexed BCD outputs isincreased by the addition of several pins which allow it tooperate in more sophisticated systems. These includeSTROBE, OVERRANGE, UNDERRANGE, RUN/HOLD andBUSY lines, making it possible to interface the circuit to amicroprocessor or UART.

Pinout

ICL7135

(PDIP)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

ICL7135CPI 0 to 70 28 Ld PDIP E28.6

V-

REFERENCE

ANALOG COMMON

INT OUT

AZ IN

BUFF OUT

REF CAP -REF CAP +

IN LO

IN HI

V+

(MSD) D5

(LSB) B1

B2

UNDERRANGE

STROBE

R/H

DIGITAL GND

POL

BUSY

D2

D3

D4

(MSB) B8

B4

OVERRANGE

CLOCK IN

(LSD) D1

28

27

26

25

24

23

2221

20

19

18

17

16

15

1

2

3

4

5

6

78

9

10

11

12

13

14

File Number 3093.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999


2/145-6

Typical Application Schematic

28

27

26

25

23

22

21

20

19

18

17

16

15

1

2

3

45

6

7

8

9

10

11

12

13

14

24

SET VREF= 1.000V

VREFIN

SIGNAL

-5V

+5V

100k

27100k

100K

ANALOGGND

INPUT

1F

0.47F

1F

0.1F

100k

ICL7135

CLOCK IN120kHz

0V

6

ANODEDRIVER

TRANSISTORS

SEVENSEG.

DECODE

DISPLAY

ICL7135


3/145-7

Absolute Maximum Ratings Thermal Information

Supply Voltage V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6VV-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V

Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to V-Reference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to V-Clock Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC

Thermal Resistance (Typical, Note 2) JA(oC/W)PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oCMaximum Storage Temperature Range . . . . . . . . . .-65oC to 150oCMaximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a st ress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:1. Input voltages may exceed the supply voltages provided the input current is limited to +100A.2. JAis measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications V+ = +5V, V- = -5V, TA= 25oC, fCLKSet for 3 Readings/s, Unless Otherwise Specified

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ANALOG (Notes 3, 4)

Zero Input Reading VlN= 0V, VREF= 1.000V -00000 +00000 +00000 Counts

Ratiometric Error (Note 4) VlN= VREF= 1.000V -3 -1 0 Counts

Linearity OverFull Scale (Error of Reading from Best Straight Line) -2VVIN+2V - 0.5 1 LSB

Differential Linearity (Difference Between Worse Case Step ofAdjacent Counts and Ideal Step)

-2VVIN+2V - 0.01 - LSB

Rollover Error (Difference in Reading for Equal Positive andNegative Voltage Near Full Scale)

-VlN+VlN2V - 0.5 1 LSB

Noise (Peak-to-Peak Value Not Exceeded 95% of Time), eN VlN= 0V, Full scale = 2.000V - 15 - V

Input Leakage Current, IILK VlN= 0V - 1 10 pA

Zero Reading Drift (Note 7) VlN= 0V, 0oC to 70oC - 0.5 2 V/oC

Scale Factor Temperature Coefficient, TC(Notes 5 and 7) VlN= +2V, 0oC to 70oC

Ext. Ref. 0ppm/oC- 2 5 ppm/ oC

DIGITAL INPUTS

Clock In, Run/Hold (See Figure 2)VINH 2.8 2.2 - V

VINL - 1.6 0.8 VIINL VIN= 0V - 0.02 0.1 mA

IINH VIN= +5V - 0.1 10 A

DIGITAL OUTPUTS

All Outputs, VOL IOL= 1.6mA - 0.25 0.40 V

B1, B2, B4, B8, D1, D2, D3, D4, D5, VOH IOH= -1mA 2.4 4.2 - V

BUSY, STROBE, OVERRANGE, UNDERRANGE, POLARITY, VOH IOH= -10A 4.9 4.99 - V

SUPPLY

+5V Supply Range, V+ +4 +5 +6 V

-5V Supply Range, V- -3 -5 -8 V

+5V Supply Current, I+ fC= 0 - 1.1 3.0 mA

-5V Supply Current, I- fC= 0 - 0.8 3.0 mA

Power Dissipation Capacitance, CPD vs Clock Frequency - 40 - pFCLOCK

Clock Frequency (Note 6) DC 2000 1200 kHz

NOTES:3. Tested in 41/2digit (20.000 count) circuit shown in Figure 3. (Clock frequency 120kHz.)4. Tested with a low dielectric absorption integrating capacitor, the 27INT OUT resistor shorted, and RlNT= 0. See Component Value Selection

Discussion.5. The temperature range can be extended to 70oC and beyond as long as the auto-zero and reference capacitors are increased to absorb

the higher leakage of the ICL7135.6. This specification relates to the clock frequency range over which the lCL7135 will correctly perform its various functions See Max Clock

Frequency section for limitations on the clock frequency range in a system.7. Parameter guaranteed by design or characterization. Not production tested.

ICL7135


4/145-8

FIGURE 1. ICL7135 TEST CIRCUIT FIGURE 2. ICL7135 DIGITAL LOGIC INPUT

FIGURE 3. ANALOG SECTION OF ICL7135

28

27

26

25

23

22

21

20

19

18

17

16

15

1

2

3

45

6

7

8

9

10

11

12

13

14

24

SET VREF= 1.000V

VREFIN

SIGNAL

-5V

+5V

100k

27100k

100K

ANALOG

GND

INPUT

1F

0.47F

1F

0.1F

100k

ICL7135

0V

CLOCKIN120kHz

UNDERRANGE

OVERRANGE

STROBE

RUN/HOLD

DIGITAL GND

POLARITY

CLOCK IN

BUSY

LSD DI

D2

D3

D4

MSB B8

B4

V-

REF

ANALOG GND

INT OUT

A-Z IN

BUF OUT

REF CAP 1

REF CAP 2

IN LO-

IN HI+

V+

MSD D5

LSB B1

B2

V+

PAD

DIG GND

CREF+ REF HI

IN HI

INT

A/Z

ANALOG

AZ

IN LO

ZI

CREF BUFFER

COMMON

INPUT

COMPARATOR

CAZ CINTRINT

INTEGRATOR

INPUT

V+

V-

POLARITY

ZERO-

LOW

HIGH

CROSSING

DETECTOR

F/F

DE(+) DE(-)

DE(-) DE(+)

AZAZ

AUTOZERO INT

1

2

3

456 11

10

9

8 7

-+

-

+

+

CREF

A/Z, DE(), ZI

INT

ICL7135


5/145-9

Detailed Description

Analog Section

Figure 3 shows the Block Diagram of the Analog Section forthe ICL7135. Each measurement cycle is divided into fourphases. They are (1) auto-zero (AZ), (2) signal-integrate(INT), (3) de-integrate (DE) and (4) zero-integrator (Zl).

Auto-Zero PhaseDuring auto-zero, three things happen. First, input high and loware disconnected from the pins and internally shorted to analogCOMMON. Second, the reference capacitor is charged to thereference voltage. Third, a feedback loop is closed around thesystem to charge the auto-zero capacitor CAZto compensatefor offset voltages in the buffer amplifier, integrator, and compar-ator. Since the comparator is included in the loop, the AZ accu-racy is limited only by the noise of the system. In any case, theoffset referred to the input is less than 10V.

Signal Integrate Phase

During signal integrate, the auto-zero loop is opened, the inter-nal short is removed, and the internal input high and low areconnected to the external pins. The converter then integratesthe differential voltage between IN HI and IN LO for a fixed time.This differential voltage can be within a wide common moderange; within one volt of either supply. If, on the other hand, theinput signal has no return with respect to the converter powersupply, IN LO can be tied to analog COMMON to establish thecorrect common-mode voltage. At the end of this phase, thepolarity of the integrated signal is latched into the polarity F/F.

De-Integrate Phase

The third phase is de-integrate or reference integrate. Inputlow is internally connected to analog COMMON and inputhigh is connected across the previously charged reference

capacitor. Circuitry within the chip ensures that the capacitorwill be connected with the correct polarity to cause the inte-grator output to return to zero. The time required for the out-put to return to zero is proportional to the input signal.Specifically the digital reading displayed is:

.

Zero Integrator Phase

The final phase is zero integrator. First, input low is shortedto analog COMMON. Second, a feedback loop is closedaround the system to input high to cause the integrator out-put to return to zero. Under normal condition, this phaselasts from 100 to 200 clock pulses, but after an overrangeconversion, it is extended to 6200 clock pulses.

Differential Input

The input can accept differential voltages anywhere within thecommon mode range of the input amplifier; or specificallyfrom 0.5V below the positive supply to 1V above the negativesupply. In this range the system has a CMRR of 86dB typical.However, since the integrator also swings with the commonmode voltage, care must be exercised to assure the integratoroutput does not saturate. A worst case condition would be alarge positive common-mode voltage with a near full scale

negative differential input voltage. The negative input signaldrives the integrator positive when most of its swing has beenused up by the positive common mode voltage. For these crit-ical applications the integrator swing can be reduced to lessthan the recommended 4V full scale swing with some loss ofaccuracy. The integrator output can swing within 0.3V of eithersupply without loss of linearity.

Analog COMMONAnalog COMMON is used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COM-MON, a common mode voltage exists in the system and istaken care of by the excellent CMRR of the converter. How-ever, in most applications IN LO will be set at a fixed knownvoltage (power supply common for instance). In this applica-tion, analog COMMON should be tied to the same point, thusremoving the common mode voltage from the converter. Thereference voltage is referenced to analog COMMON.

Reference

The reference input must be generated as a positive voltagewith respect to COMMON, as shown in Figure 4.

Digital Section

Figure 5 shows the Digital Section of the ICL7135. TheICL7135 includes several pins which allow it to operate con-veniently in more sophisticated systems. These include:

Run/HOLD (Pin 25)

When high (or open) the A/D will free-run with equallyspaced measurement cycles every 40,002 clock pulses. Iftaken low, the converter will continue the full measurementcycle that it is doing and then hold this reading as long asR/H is held low. A short positive pulse (greater than 300ns)will now initiate a new measurement cycle, beginning withbetween 1 and 10,001 counts of auto zero. If the pulseoccurs before the full measurement cycle (40,002 counts)is completed, it will not be recognized and the converter willsimply complete the measurement it is doing. An externalindication that a full measurement cycle has been com-pleted is that the first strobe pulse (see below) will occur101 counts after the end of this cycle. Thus, if Run/HOLD islow and has been low for at least 101 counts, the converteris holding and ready to start a new measurement whenpulsed high.

STROBE (Pin 26)

This is a negative going output pulse that aids in transferringthe BCD data to external latches, UARTs, or microproces-sors. There are 5 negative going STROBE pulses that occurin the center of each of the digit drive pulses and occur onceand only once for each measurement cycle starting 101clock pulses after the end of the full measurement cycle.Digit 5 (MSD) goes high at the end of the measurementcycle and stays on for 201 counts. In the center of this digitpulse (to avoid race conditions between changing BCD anddigit drives) the first STROBE pulse goes negative for 1/2clock pulse width. Similarly, after digit 5, digit 4 goes high (for200 clock pulses) and 100 pulses later the STROBE goesnegative for the second time. This continues through digit 1(LSD) when the fifth and last STROBE pulse is sent. The

OUTPUT COUNT 10,000VIN

VRE F---------------

=

ICL7135


6/145-10

digit drive will continue to scan (unless the previous signalwas overrange) but no additional STROBE pulses will besent until a new measurement is available.

BUSY (Pin 21)

BUSY goes high at the beginning of signal integrate and stayshigh until the first clock pulse after zero crossing (or after end ofmeasurement in the case of an overrange). The internal latches

are enabled (i.e., loaded) during the first clock pulse after busyand are latched at the end of this clock pulse. The circuit auto-matically reverts to auto-zero when not BUSY, so it may also beconsidered a (Zl + AZ) signal. A very simple means for transmit-ting the data down a single wire pair from a remote locationwould be to AND BUSY with clock and subtract 10,001 countsfrom the number of pulses received - as mentioned previouslythere is one NO-count pulse in each reference integrate cycle.

OVERRANGE (Pin 27)

This pin goes positive when the input signal exceeds therange (20,000) of the converter. The output F/F is set at theend of BUSY and is reset to zero at the beginning of refer-ence integrate in the next measurement cycle.

UNDERRANGE (Pin 28)This pin goes positive when the reading is 9% of range orless. The output F/F is set at the end of BUSY (if the newreading is 1800 or less) and is reset at the beginning of sig-nal integrate of the next reading.

POLARlTY (Pin 23)

This pin is positive for a positive input signal. It is valid evenfor a zero reading. In other words, +0000 means the signal ispositive but less than the least significant bit. The convertercan be used as a null detector by forcing equal frequency of(+) and (-) readings. The null at this point should be less than0.1 LSB. This output becomes valid at the beginning of refer-ence integrate and remains correct until it is revalidated for

the next measurement.

Digit Drives (Pins 12, 17, 18, 19 and 20)

Each digit drive is a positive going signal that lasts for 200 clockpulses. The scan sequence is D5 (MSD), D4, D3, D2, and D1

(LSD). All five digits are scanned and this scan is continuousunless an overrange occurs. Then all digit drives are blankedfrom the end of the strobe sequence until the beginning of Ref-erence Integrate when D5 will start the scan again. This cangive a blinking display as a visual indication of overrange.

BCD (Pins 13, 14, 15 and 16)

The Binary coded Decimal bits B8, B4, B2, and B1 are positive

logic signals that go on simultaneously with the digit driver signal.

FIGURE 4A.

FIGURE 4B.

FIGURE 4. USING AN EXTERNAL REFERENCE

IZ

6.8V

V-

ZENERREF HI

ICL7135

COMMON

V+

6.8k

ICL8069REF HI

ICL7135

COMMON

V+

V+

20k1.2VREFERENCE

V+ POLARITY

DIGITAL CLOCK RUN/ BUSYOVER STROBEUNDER

MULTIPLEXERANALOG

GND IN HOLD RANGE RANGE

SECTION

MSB LSB

CONTROL LOGIC

COUNTERSZERO

CROSS.DET.

POLARITYFF LATCH LATCH LATCH LATCHLATCH

11 23 12 17 18 19 20

24 22 2725 28 26 21

13

14

15

16

D1D2D3D4

B1

B2

B4

B8

D5

FIGURE 5. DIGITAL SECTION OF THE ICL7135

ICL7135


7/145-11

Component Value Selection

For optimum performance of the analog section, care mustbe taken in the selection of values for the integrator capacitorand resistor, auto-zero capacitor, reference voltage, andconversion rate. These values must be chosen to suit theparticular application.

Integrating Resistor

The integrating resistor is determined by the full scale inputvoltage and the output current of the buffer used to chargethe integrator capacitor. Both the buffer amplifier and theintegrator have a class A output stage with 100A of quies-cent current. They can supply 20A of drive current withnegligible non-linearity. Values of 5A to 40A give goodresults, with a nominal of 20A, and the exact value of inte-grating resistor may be chosen by:

.

Integrating Capacitor

The product of integrating resistor and capacitor should beselected to give the maximum voltage swing which ensuresthat the tolerance built-up will not saturate the integratorswing (approx. 0.3V from either supply). For 5V suppliesand analog COMMON tied to supply ground, a3.5V to4Vfull scale integrator swing is fine, and 0.47F is nominal. Ingeneral, the value of ClNT is given by:

,

.

A very important characteristic of the integrating capacitor isthat it has low dielectric absorption to prevent roll-over orratiometric errors. A good test for dielectric absorption is touse the capacitor with the input tied to the reference.

This ratiometric condition should read half scale 0.9999, andany deviation is probably due to dielectric absorption.Polypropylene capacitors give undetectable errors at reason-able cost. Polystyrene and polycarbonate capacitors mayalso be used in less critical applications.

Auto-Zero and Reference Capacitor

The physical size of the auto-zero capacitor has an influenceon the noise of the system. A larger capacitor value reduces

system noise. A larger physical size increases system noise.The reference capacitor should be large enough such thatstray capacitance to ground from its nodes is negligible.

The dielectric absorption of the reference cap and auto-zerocap are only important at power-on or when the circuit isrecovering from an overload. Thus, smaller or cheaper capscan be used here if accurate readings are not required forthe first few seconds of recovery.

Reference Voltage

The analog input required to generate a full scale output isVlN= 2VREF.

The stability of the reference voltage is a major factor in theoverall absolute accuracy of the converter. For this reason, itis recommended that a high quality reference be used wherehigh-accuracy absolute measurements are being made.

Rollover Resistor and Diode

A small rollover error occurs in the ICL7135, but this can beeasily corrected by adding a diode and resistor in seriesbetween the INTegrator OUTput and analog COMMON orground. The value shown in the schematics is optimum forthe recommended conditions, but if integrator swing or clockfrequency is modified, adjustment may be needed. Thediode can be any silicon diode such as 1N914. These com-ponents can be eliminated if rollover error is not importantand may be altered in value to correct other (small) sourcesof rollover as needed.

Max Clock Frequency

The maximum conversion rate of most dual-slope A/D con-verters is limited by the frequency response of the compara-tor. The comparator in this circuit follows the integrator rampwith a 3s delay, and at a clock frequency of 160kHz (6speriod) half of the first reference integrate clock period is lostin delay. This means that the meter reading will change from0 to 1 with a 50V input, 1 to 2 with a 150V input, 2 to 3with a 250V input, etc. This transition at mid-point is consid-ered desirable by most users; however, if the clock fre-quency is increased appreciably above 160kHz, theinstrument will flash 1 on noise peaks even when the inputis shorted.

For many dedicated applications where the input signal is

always of one polarily, the delay of the comparator need notbe a limitation. Since the non-linearity and noise do notincrease substantially with frequency, clock rates of up to~1MHz may be used. For a fixed clock frequency, the extracount or counts caused by comparator delay will be constantand can be subtracted out digitally.

The clock frequency may be extended above 160kHzwithout this error, however, by using a low value resistor inseries with the integrating capacitor. The effect of the resis-tor is to introduce a small pedestal voltage on to the integra-tor output at the beginning of the reference integrate phase.By careful selection of the ratio between this resistor and theintegrating resistor (a few tens of ohms in the recommendedcircuit), the comparator delay can be compensated and themaximum clock frequency extended by approximately a fac-tor of 3. At higher frequencies, ringing and second orderbreaks will cause significant non-linearities in the first fewcounts of the instrument. See Application Note AN017.

The minimum clock frequency is established by leakage onthe auto-zero and reference caps. With most devices, mea-surement cycles as long as 10s give no measurable leakageerror.

RIN Tfull scale voltage

20A--------------------------------------------=

CIN T10,000 clock period IIN T

integrator output voltage swing----------------------------------------------------------------------------------

=

(10,000) (clock period) (20A)integrator output voltage swing---------------------------------------------------------------------------------=

ICL7135


8/14


9/145-13

driven from the 7 segment decoder, with a zero readingblanked by connecting a D5 signal to RBl input of thedecoder. The 2-gate clock circuit should use CMOS gates tomaintain good power supply rejection.

A suitable circuit for driving a plasma-type display is shownin Figure 8. The high voltage anode driver buffer is made byDionics. The 3 AND gates and caps driving BI are neededfor interdigit blanking of multiple-digit display elements, andcan be omitted if not needed. The 2.5k and 3kresistorsset the current levels in the display. A similar arrangementcan be used with Nixietubes.

The popular LCD displays can be interfaced to the outputs ofthe ICL7135 with suitable display drivers, such as theICM7211A as shown in Figure 9. A standard CMOS 4030QUAD XOR gate is used for displaying the 1/2 digit, thepolarity, and an overrange flag. A similar circuit can beused with the ICL7212A LED driver and the ICM7235A vac-uum fluorescent driver with appropriate arrangements madefor the extra outputs. Of course, another full driver circuitcould be ganged to the one shown if required. This would beuseful if additional annunciators were needed. The Figure

shows the complete circuit for a 41/2digit (2.000V) A/D.Figure 10 shows a more complicated circuit for driving LCDdisplays. Here the data is latched into the ICM7211 by theSTROBE signal and Overrange is indicated by blanking the4 full digits.

A problem sometimes encountered with both LED andplasma-type display driving is that of clock source supplyline variations. Since the supply is shared with the display,any variation in voltage due to the display reading maycause clock supply voltage modulation. When in overrangethe display alternates between a blank display and the 0000overrange indication. This shift occurs during the referenceintegrate phase of conversion causing a low display reading

just after overrange recovery. Both of the above circuits haveconsiderable current flowing in the digital supply from driv-ers, etc. A clock source using an LM311 voltage comparatorwith positive feedback (Figure 11) could minimize any clockfrequency shift problem.

The ICL7135 is designed to work from5V supplies. How-ever, if a negative supply is not available, it can be generatedwith an ICL7660 and two capacitors (Figure 12).

Interfacing with UARTs andMicroprocessors

Figure 13 shows a very simple interface between a

free-running ICL7135 and a UART. The five STROBE pulsesstart the transmission of the five data words. The digit 5 wordis 0000XXXX, digit 4 is 1000XXXX, digit 3 is 0100XXXX, etc.Also the polarity is transmitted indirectly by using it to drivethe Even Parity Enable Pin (EPE). If EPE of the receiver isheld low, a parity flag at the receiver can be decoded as apositive signal, no flag as negative. A complex arrangementis shown in Figure 14. Here the UART can instruct the A/D tobegin a measurement sequence by a word on RRl. TheBUSY signal resets the Data Ready Reset (DRR). AgainSTROBE starts the transmit sequence. A quad 2 input

multiplexer is used to superimpose polarity, over-range, andunder-range onto the D5 word since in this instance it isknown that B2 = B4 = B8 = 0.

For correct operation it is important that the UART clock befast enough that each word is transmitted before the nextSTROBE pulse arrives. Parity is locked into the UART atload time but does not change in this connection during anoutput stream.

Circuits to interface the ICL7135 directly with three popularmicroprocessors are shown in Figure 15 and Figure 16. The8080/8048 and the MC6800 groups with 8-bit buses need tohave polarity, over-range and under-range multiplexed ontothe Digit 5 Sword - as in the UART circuit. In each case themicroprocessor can instruct the A/D when to begin a mea-surement and when to hold this measurement.

Application Notes

NOTE # DESCRIPTION

AnswerFAX

DOC. #

AN016 Selecting A/D Converters 9016AN017 The Integrating A/D Converter 9017

AN018 Dos and Donts of Applying A/DConverters

9018

AN023 Low Cost Digital Panel Meter Designs 9023

AN028 Building an Auto-Ranging DMM Usingthe 8052A/7103A A/D Converter Pair

9028

AN030 The ICL7104 - A Binary Output A/DConverter for Microprocessors

9030

AN032 Understanding the Auto-Zero andCommon Mode Performance of theICL7136/7/9 Family

9032

ICL7135


10/145-14

FIGURE 7. 41/2DIGIT A/D CONVERTER WITH A MULTIPLEXED COMMON ANODE LED DISPLAY

FIGURE 8. ICL7135 PLASMA DISPLAY CIRCUIT FIGURE 9. LCD DISPLAY WITH DIGIT BLANKING ON

OVERRANGE

ANALOGGND

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27

26

25

2423

22

21

20

19

18

17

16

15

1

2

3

4

56

7

8

9

10

11

12

13

14

+5V

6.8k VREF=

SIGNAL

0.1F

-5V

ICL8069 1

2

5

B1BA

7447

34

B2C

DE

FG

B4B8

C RC NETWORK

OSC= 0 .45/RC

1.000V

10k

100k

27

47K

150

INPUT

1F

R

RBI

100k

+5V

100K

1F0.47F

2 1

150

150

4.7K

+5V

ICL7135V-

REFANALOG

INT OUT

AZIN

BUF OUT

RC1

RC2

INPUT LO

INPUT HI

V+

D5

B1

B2

UR

OR

STROBE

R/H

DIG. GNDPOL

CLOCK

BUSY

D1

D2

D3

D4

B8

B4

COMMON

(NOTE 1)

NOTE:

1. For finer resolution on scale factor adjust, use a 10 turn pot or a small pot in series witha fixed resistor.

B1

47K

0.02F

A

G

D

B8D1

2.5K

DM

RBI

8880

HI VOLTAGE BUFFER D1 505

ICL7135

5K

+5V

POL D5

RB0

AA

G

0.02F

POL

GATES

0V

PROG

ARE7409

+5

3K

V+ +5

0VBI

0.02F

0

.02F

0.02F

V+

DGND

28 B1

26 STROBE

14 B2

13 B1

12 D5

27 OR

CD4011

+5V1/4CD4030

ICL7135

ICM7211A

15 B4

16 B8

17 D4

19 D2

20 D1

23 POL

CD4081

CD4071

27 B0

29 B2

34 D4

33 D3

30 B3

32 D2

5 BP

31 D1

18 D3

+5V

BP

1/2CD4030

41/2DIGIT LCD DISPLAY

1/4 CD4030

ICL7135


11/145-15

FIGURE 10. DRIVING LCD DISPLAYS

FIGURE 11. LM311 CLOCK SOURCE FIGURE 12. GENERATING A NEGATIVE SUPPLY FROM +5V

20

28

27

26

25

24

23

22

21

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

REF

-5V

ANALOG

27

0.47F

1F

100k

INPUT

+5V

ICL7135

CD4054A

120kC = 3 READINGS/SECCLOCK IN

BACKPLANE

41/2DIGIT LCD DISPLAY28 SEGMENTS D1-D4

OPTIONAL

2,3,4

ICM7211A

300pF

0V

22-100pF

VOLTAGE

GND

CAPACITOR

6-26

V-

REFANALOG

INT OUT

AZIN

BUF OUT

RC1

RC2

INPUT LO

INPUT HI

V+

D5

B1

B2

37-40

OSC 36

V+ 1

UR

OR

STROBE

R/H

DIG. GND

POL

CLOCK

BUSY

D1

D2

D3

D4

B8

B4

1

31 D1

32 D2

33 D3

34 D4

30 B3

29 B2

28 B1

27 B035 V-

16 15 14 12 5 3 4

7 8 131110 9 2 6

+5V

+5V

+5V

0.1F

1F

100k

COMMON

5BP

100k

0.22F

16k56k

+5V

1k

30k

390pF

13 4

8

7

16k

LM311

+2

-

1

2

3

4

7

6

5

8

10F-

+

+5V

VOUT= -5V

ICL7660

10F-+

ICL7135


12/145-16

FIGURE 13. ICL7135 TO UART INTERFACE FIGURE 14. COMPLEX ICL7135 TO UART INTERFACE

FIGURE 15. ICL7135 TO MC6800, MCS650X INTERFACED FIGURE 16. ICL7135 TO MCS-48, -80, -85 INTERFACE

EPE

POL

D5

ICL7135

NC

RUN/HOLD

STROBE

TBR

TBRL

+5V

D4 D3 D2 D1 B1 B2 B4

TRO

B8

1 2 3 4 5 6 87

UART

SERIAL OUTPUTTO RECEIVING UART

IM6402/3

1A 2A 3A

B4B2B1

1B 2B 3B

2 3 4

D2D3

D5

876

D1

5

1Y 2Y 3Y

1

B8

POL

OVER

UNDER

SELECT

RUN/HOLD

STROBE

BUSY

ICL7135

ENABLE

IM6402/3

TRO RRI DRRDR

TBRLEPE

+5V

100pF 10K

74C157

TBR

D4

EN

74C157

1B 2B 3B 1A 2A 3A

1Y

2Y

3Y

B1D5 B8 B4 B2

D1

D2

D3

D4

ICL7135

1Y PA0

PA1

PA2

PA4

PA5

PA6

PA7

POL

OVER

UNDER

SELECT

RUN/HOLD STROBE

CA1 CA2

MC6820

MC680XOR

MCS650XPA3

EN

74C157

1B 2B 3B 1A 2A 3A

1Y

2Y

3Y

B1D5 B8 B4 B2

D1

D2

D3

D4

ICL7135

1Y PA0

PA1

PA2

PA4

PA5

PA6

PA7

POL

OVER

UNDER

SELECT

RUN/HOLD STROBE

STBA PB0

8255(MODE1)

80C488080

8085,ETC.PA3

ICL7135


13/145-17

Typical Integrator Amplifier Output Waveform (INT Pin)

Design Information Summary Sheet

CLOCK INPUT

The ICL7135 does not have an internal oscillator. Itrequires an external clock.fCLOCK(Typ) = 120kHz

CLOCK PERIOD

tCLOCK= 1/fCLOCK

INTEGRATION PERIOD

tINT= 10,000 x tCLOCK

60/50Hz REJECTION CRITERION

tINT/ t60Hzor tINT/ t50Hz= Integer

OPTIMUM INTEGRATION CURRENT

IINT= 20A

FULL-SCALE ANALOG INPUT VOLTAGE

VlNFS(Typ) = 200mV or 2V

INTEGRATE RESISTOR

INTEGRATE CAPACITOR

INTEGRATOR OUTPUT VOLTAGE SWING

VINTMAXIMUM SWING:

(V- + 0.5) < VINT< (V+ - 0.5V)VINTTypically = 2.7V

DISPLAY COUNT

CONVERSION CYCLE

tCYC= tCL0CKx 40002when fCLOCK= 120kHz, tCYC= 333ms

COMMON MODE INPUT VOLTAGE

(V- + 1V) < VlN< (V+ - 0.5V)

AUTO-ZERO CAPACITOR

0.01F < CAZ< 1F

REFERENCE CAPACITOR

0.1F < CREF< 1F

POWER SUPPLY: DUAL5V

V+ = +5V to GND

V- = -5V to GND

OUTPUT TYPE

4 BCD Nibbles with Polarity and Overrange Bits

There is no internal reference available on the ICL7135. Anexternal reference is required due to the ICL7135s 41/2digit resolution.

RIN TVINFSIIN T

-----------------=

CIN TtIN T( ) IIN T( )

VIN T--------------------------------=

VIN TtIN T( ) IIN T( )

CIN T--------------------------------=

COUNT 10 000,VIN

VREF-----------------=

AUTO ZERO PHASE(COUNTS)

30001 - 10001

INTEGRATEPHASE FIXED

10000 COUNTS

DE-INTEGRATE PHASE1 - 20001 COUNTS

TOTAL CONVERSION TIME = 40002 x tCLOCK

ICL7135


14/14

Die Characteristics

DIE DIMENSIONS:

(120 mils x 130 mils) x 525m25m

METALLIZATION:

Type: Al

Thickness: 10k1k

PASSIVATION:

Type: Nitr ide/Silox SandwichThickness: 8k Nitride over 7k Silox

Metallization Mask Layout

ICL7135

V+ IN HI IN LOREF REFCAP+ CAP+

BUFFOUT

AZIN

INT OUT

ANALOG COMMON

REFERENCE

V-

UNDERRANGE

OVERRANGE

STROBE

R/HDIGITALPOLCLOCK INGND

BUSY(LSD)D1D2

(MSD) D5

(LSB) B1

B2

B4

(MSB) B8

D4

D3

ICL7135

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000quality systems certification.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate

and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which

may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

datasheet icl7135

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