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Shubhankar Majumdar, Muhammad Khalid / International Journal of Engineering Research

and Applications (IJERA) ISSN: 2248-9622 www.ijera.com

Vol. 2, Issue 6, November- December 2012, pp.822-826

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A Novel Sequence Generator Replacing LFSR For Hardwired

BIST Of SRAM

Shubhankar Majumdar*, Muhammad Khalid**

*(Department of Electronics & Instrumentation, S.G.S.I.T.S, Indore, M.P.)** (Department of Electrical & Electronics Engineering, Galgotias College of Engg. & Tech., Gr.Noida , U.P)

ABSTRACTThis paper has emphasis on the novel sequence

generation for the hardwired built in self test

(BIST) of static random access memory (SRAM).

It reduces the testing time of SRAM bygenerating all the pattern sequence in less time. BIST is a design technique that allows a circuit to

test itself. Linear feedback shift register (LFSR)

was used for the sequence generation in the BIST

but novel sequence generator is better than LFSRfor BIST of SRAM. The novel designing of the

sequence generator has done with the help of

synchronous up and down counter. The up and

down counter has used here is of 4 bits and the

corresponding addresses are also of 4 bits but

there is a unique transition take place. Theswitching between the sequence of the up and

down counter generates the sequence which is

fulfilling the requirement for the BIST purpose.

This requires very little hardware overhead so the

area is reduced which on the other hand reduced

cost as well as power. The necessary sequences

which have required for detecting the faults suchstuck at/open faults, transition faults, etc. It can

be detected easily with the help of this sequence

generator.

The large number of sequences can be

generated with the help of cascading the smallermodule. It is more efficient than LFSR. The

whole designing has done in the 180 nm

technology in Cadence’s spectre, virtuoso &

assura tool.

Keywords – BIST, LFSR, SRAM, sequence

generator, and counter.

I. INTRODUCTIONA LFSR is a shift register whose input is theexclusive-or of some of its outputs. The outputs that

influence the input are called taps.[1] A maximalLFSR produces an n-sequence, unless it contains allzeros. The tap sequence of a LFSR can be

represented as a polynomial mod 2 - called thefeedback polynomial. [2] LFSR's can beimplemented in hardware. The designing of the shiftregister is done by the help of D flip-flop. A 4bit

LFSR generates the sequence of 0000, 0001, 0010,0011…up to 1111. This sequence has the transition

from 0-1 and 1-0 of the bits.

The problem in using the LFSR in the BIST designwas that the extra sequences which are generated by

the LFSR which consumes the power and loweredthe speed of the testing this simultaneously degradethe performance of peripherals used for testing. [3]In the testing of memory the transition of the 1 to 0and 0 to 1 is needed which is generated by thesequence generator properly but on the other hand

the LFSR generates the various sequences which arenot needed for the detection purpose.

Figure 1. Simplified circuit of a generic n-bit LFSR.

Hardware implementation of the PRBGs isalmost always made up of the well-known linear-feedback shift register (LFSR) [5], whose genericcircuit is reported in Figure 1. Simplified circuit of a

generic n-bit LFSR are useful in many areas of digital design and science.[2] LFSR is the mostcommon used topology to implement PRBG. It is

obtained with an array of FFs with a linear feedback performed by several XOR gates. They are based ona rather complex mathematical theory [6]. A 3-stage

LFSR is characterized by its feedback polynomial[4]-[11]

P (x) = 1 + x2 + x3 … (i)

Various works has been done on thearchitecture design of the LFSR. The work which

has done in this paper is novel. This sequencegenerator is the replacement of the LFSR inhardwired SRAM BIST. This will give a new

direction for the fast and synchronized sequencegeneration for the BIST applications. This paperdescribes how the sequence generation is done bythis novel circuit.

II. SEQUENCE GENERATOR

The sequence generated by the sequence generatoris done by also gives this transition of bits. Thesequences which are generated by this sequence

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generator are as follows 0000, 1111, 0001, 1110,0010, 1101, 0011,1100,0100,1011, 0101, 1010,0110, 1001, 0111 and 1000.

The sequence generator is formed by thehelp of up and down counter, the sequence switchesfrom the up counter sequence to down countersequence with the help of a switching circuit.

Switching from the up counter sequence to downcounter is done by the conventional circuit. Theconventional circuits are used here so the delay is

less which corresponds to the increases in the speed.As soon as the input will change the output will alsochange accordingly. So the fast sequence generationcan be done easily. On the other hand a huge testing

sequence are not required because the neededtransition from 1-0 & 0-1 is got by small numbers of

sequences hence it produce chance to decrease thetesting time of the SRAM.

It is useful for a huge number of inputsbecause by the help of the cascading we cangenerate the necessary transitions for the testing

purpose.

III. PARTS OF SEQUENCE GENERATOR There has a combination of up and down Counter.The designing of the up counter (4bit) is done by the

help of the JK flip flop and NAND gate forresetting. The resetting of the up counter is neededbecause there is only need to count 0 to 7. Similarly,the down counter (4bit) is done by the help of the JKflip flop and AND gate for resetting. The presettingof the down counter is needed because there is only

need to count F to 8.In this way the counter has been designed which hasa control signal. It controls the up and down counterby switching the up and down counter alternatively.

That means when the control signal is high the upcounter’s output goes to the output and when the

control signal is low the down counter’s output goesto the output. By the help of this procedure only the

bit sequence of 0, F, 1, E, 2, D, 3, C, 4, B, 5, A, 6, 9,

7, 8 can be achieved.The sequences can be generated for 8 bit counter bycascading the resultant 4 bit counter results. For 8bitthe sequence is as follows 00, FF, 11, EE, 22, DD,33, CC, 44, BB, 55, AA, 66, 99, 88, 77.

IV DESIGN OF CIRCUITS IV.I SCHEMATIC DESIGN OF CIRCUITS

IV.I.I UP COUNTERThe up counter designing deals with the integrationof the JK flip-flop and the 4 bit NAND gate forresetting purpose. In this circuit only one input pin

and four output pins they are Q0, Q1, Q2 & Q4. The

below shown diagram give the detailed view of thecircuit of the up counter.

FIG. IV.I.I schematic design of up counter

IV.I.II DOWN COUNTER The down counter designing deals with the

integration of the JK flip-flop and the 4 bit ANDgate for presetting purpose. In this circuit only one

input pin and four output pins they are Q0, Q1, Q2 &Q4. The below shown diagram give the detailedview of the circuit of the up counter.

FIG. IV.I.II schematic design of down counter

IV.I.III SEQUENCE GENERATOR The design of the sequence generator has done bythe help of alternating turning on the up counter and

down counter with the help of the switching circuit,as shown below.

FIG. IV.I.III schematic design of sequence generator

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IV.II TEST BENCH OF CIRCUITSThe test bench shows the biasing of the circuits andit is useful for taking the simulated responses of the

circuit.

IV.II.I UP COUNTER

FIG. IV.II.I Test Bench of up counter circuit

IV.II.II DOWN COUNTER

FIG. IV.II.II Test Bench of down counter circuit

IV.II.III SEQUENCE GENERATOR

FIG. IV.II.III Test Bench of sequence generator

IV.III LAYOUT OF CIRCUITS The layout of the blocks and the pattern sequenceare as follows.

IV.III.I UPCOUNTER

FIG. IV.III.I Layout of up counter

IV.III.II DOWN COUNTER

FIG. IV.III.II Layout of down counter

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IV.III.III SEQUENCE GENERATOR

FIG. IV.III.III Layout of sequence generator

V. SIMULATION AND RESULTS

V.I UP COUNTER The simulation of the up and down counters is asfollows

FIG. V.I Simulated Result of up counter

V.II DOWN COUNTER

FIG. V.II Simulated Result of down counter

V.III SEQUENCE GENERATOR The whole sequence generator is designed by thehelp of the counters. The sequences of the addressare shown below. The 4bit output of the counter is

given in which it can be seen that the sequence

follows as 0, F, 1, E, 2, D, 3, C, 4, B, 5, A, 6, 9, 8, 7respectively. The simulation results of the sequencegenerator are as follows

FIG. V.I Simulated Result of Sequence Generator

VI. TABULATED RESULTSThe below results shows the power and area whichis calculated by spectre and virtuoso tools

respectively.

VII. CONCLUSION The sequence generator has comparatively lowerpower and area with respect to LFSR. The testingtime of SRAM is reduced by the help of this

sequence generator because all the pattern sequencewhich has required for testing are generated in lessduration of time. As we say that for 8 address the

LFSR generates 28

sequences but the patterngenerator used by cascading. It can produce 16sequences which is sufficient for testing. The powerand area of whole BIST circuit is given as 440µWand 0.0556mm

2.

REFERENCES [1] Bardel, McAnney, and Savir, “ Built-In Test

for VLSI: Pseudorandom Techniques, ” John Wiley and Sons, 1987.

[2] L.Wang and E. J. McCluskey, “Circuits for

Pseudo exhaustive test pattern generation,”IEEE Trans.Comput.-Aided Des., vol. 7,

no. 10, pp.1068 – 1080, Oct. 1988. [3] M. Lowy, “Parallel implementation of

linear feedback shift register for low power

applications,” IEEE Trans. CircuitsSyst. II,

Analog Digit. Signal Process., vol. 43, no.6, Jun.1996.

S. No. Component Power Area

1 Up-Counter 255µW 0.0085mm2

2 Down-Counter 292µW 0.024mm2

3SequenceGenerator

440µW 0.0556mm2

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[4] Dipert, Brian, “Shattering the programmable-logic speed barrier,” EDN ,May 22, 1997, pg 37.

[5] T. Lang, E. Musoll, and J. Cortadella,

“ Individual flip-flops with gated clocks for low power data paths,” IEEE

Trans.Circuits Syst. II, Analog Digit.Signal Process, vol. 44, no. 6,pp. 507 – 516,

Jun. 1997.[6] M. E. Hamid and C. H. Chen, “ A note to

low-power linearfeedback shift registers,”

IEEE Trans. Circuits Syst. II, Analog Digit.Signal Process, vol. 45, no. 9, pp. 1304 –

1307, Sep.1998.[7] R.David, “ Random Testing of Digital

Circuits. Theory and Application,” NewYork: Marcel Dekker, 1998.

[8] Al-Asaad & Mayank Shringi, ” Builtin Self-Test For operational Fault s,”IEEE Design

& Test of Computers, Vol.15, No. 4, pp.17- 24, November 1998

[9] L. Benini, A. Bogliolo, and G. D. Micheli,“ A survey of design techniques for system-level dynamic power management ,” IEEETrans. Very Large Scale Integr. (VLSI)

Syst., vol. 8, no. 3, pp. 299 – 316, Jun. 2000.[10] G. Palumbo, F. Pappalardo, and S.

Sannella, “ Evaluation on power reduction

applying gated clock approach,”

Proc.IEEE ISCAS 2002, vol. 44, pp. IV85 –

IV88, May 2002.[11] R. S. Katti, X. Ruan, and H. Khattri,

“ Multiple-Output low power linear

feedback shift register design,” IEEETrans. Circuits Syst. I,Reg. Papers, vol. 53,no. 7, pp. 1487 – 1495, Jul. 2006.

Author’s Profile SHUBHANKAR MAJUMDAR

He has received the B.E. degree in Electronics andCommunication Engineering from University

Institute of Technology (U.I.T R.G.P.V) RajivGandhi Technical University, Bhopal, India in 2010.He has completed M.Tech degree in Micro--

electronics and VLSI Design from S.G.S.I.T.S.Indore, India in 2012.

MUHAMMAD KHALID

He has received the B.Tech. degree in Electronicsand Communication Engineering from UttarPradesh Technical University, India in 2007, DESDfrom C-DAC Mohali, India in 2008 and M.Tech.Degree in Electronics Circuits & System Designfrom Aligarh Muslim University (A.M.U), Aligarh,

India in 2010. He is now working as AssistantProfessor in Department of Electrical & ElectronicsEngineering, Galgotias College of Engineering &

Technology, Gr. Noida , U.P, India. His interest of research is in Analog and digital system design.

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