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1 Seat No.: ________ Enrolment No.______________ GUJARAT TECHNOLOGICAL UNIVERSITY Diploma Engineering - SEMESTER – IV • EXAMINATION – WINTER 2012 Subject code: 340702 Date: 26/12/2012 Subject Name: Computer Organization & Architecture Time: 02.30 pm - 05.00 pm Total Marks: 70 Instructions: 1. Attempt any five questions. 2. Make suitable assumptions wherever necessary. 3. Figures to the right indicate full marks. 4. English version is considered to be Authentic. Q.1 (a) Explain Bus system Data transfer for five Registers using Multiplexers. 07 (b) Explain with illustrations, difference between Macro & Micro instruction. 07 Q. 2 (a) Give the list of registers in basic computer organization & memory bank with their sizes. Draw the register organization with memory. 07 (b) Write & explain fetch & execute phase of following memory reference instructions: ADD and LDA. 07 OR (b) How the Control unit of Basic Computer is designed? 07 Q. 3 (a) Explain different parts of General register (Bus Organized) CPU. 07 (b) Explain with comparison, which one is batter than other among RICS & CICS. 07 OR Q.3 (a) Explain and compare different instruction formats (From Zero to Three Address fields) by solving following arithmetic statement: A = (B * C) + (D / E). 07 (b) Explain the use of stack organized CPU with diagrams. 07 Q. 4 (a) Draw and explain each block of general organization of micro programmed control system. 07 (b) Draw and explain hardware configuration of micro programmed control organization. 07 OR Q. 4 (a) Explain parallel organization having multiple functional units with diagram. 07 (b) Explain four segments Instruction pipeline with flow chart. 07 Q. 5 (a) What is Speedup in pipe line computing? Show S (Speedup) = K (No. of Segments) is true. 07 (b) Write short note on Pipeline conflicts. 07 OR Q.5 (a) Give the differences of Synchronous & Asynchronous data transfer. 07 (b) What is ’Write Through’ & ‘Write Back’ in Cache memory. 07 ************

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Seat No.: ________ Enrolment No.______________

GUJARAT TECHNOLOGICAL UNIVERSITY Diploma Engineering - SEMESTER – IV • EXAMINATION – WINTER 2012

Subject code: 340702 Date: 26/12/2012 Subject Name: Computer Organization & Architecture Time: 02.30 pm - 05.00 pm Total Marks: 70 Instructions:

1. Attempt any five questions. 2. Make suitable assumptions wherever necessary. 3. Figures to the right indicate full marks. 4. English version is considered to be Authentic.

Q.1 (a) Explain Bus system Data transfer for five Registers using Multiplexers. 07

(b) Explain with illustrations, difference between Macro & Micro instruction.

07

Q. 2 (a) Give the list of registers in basic computer organization & memory bank

with their sizes. Draw the register organization with memory. 07

(b) Write & explain fetch & execute phase of following memory reference instructions: ADD and LDA.

07

OR (b) How the Control unit of Basic Computer is designed? 07

Q. 3 (a) Explain different parts of General register (Bus Organized) CPU. 07 (b) Explain with comparison, which one is batter than other among RICS &

CICS. 07

OR Q.3 (a) Explain and compare different instruction formats (From Zero to Three

Address fields) by solving following arithmetic statement: A = (B * C) + (D / E).

07

(b) Explain the use of stack organized CPU with diagrams. 07

Q. 4 (a) Draw and explain each block of general organization of micro programmed control system.

07

(b) Draw and explain hardware configuration of micro programmed control organization.

07

OR Q. 4 (a) Explain parallel organization having multiple functional units with

diagram. 07

(b) Explain four segments Instruction pipeline with flow chart. 07

Q. 5 (a) What is Speedup in pipe line computing? Show S (Speedup) = K (No. of Segments) is true.

07

(b) Write short note on Pipeline conflicts. 07 OR

Q.5 (a) Give the differences of Synchronous & Asynchronous data transfer. 07 (b) What is ’Write Through’ & ‘Write Back’ in Cache memory. 07

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2

. 1 અ પાચં ર જ ટર માટ મ ટ લ રનો ઉપયોગ કર ન ડટા ાસંફર માટની ે ે

બસ ણા લ સમ વો.

07

બ મ ો તથા માઈ ો ે સ શન વચનો તફાવત ઉદાહરે ણ સાથ સમ વોે . 07

. 2 અ બઝીક કો ટર બધંારણમા ંમમર બક સાથ બધાજ ર જ ટરો ંલીે ે ેુ ુ ટ

આપો તથા દરકની સાઇઝ આપો. મમર સાથ ર જ ટરોની ગોઠવણીે ે દોર

બતાવો.

07

બ ફચ તથા એ સી ટ ત બકાઓ નીચ જણાવલ મમર ુ ે ે ે ર સ ં સ શન

માટ લખો તથા સમ વો: ADD તથા LDA.

07

અથવા

બ બઝીક કો ટર ંકં ોલ િનટ ે ુ ુ ુ કવી ર ત બનાવ ંહોઈ છે ે ેુ ? 07

. 3 અ જનરલ ર જ ટર(બસ ઓગનાઈ ડ) સીપી નુા દા દા ભાગો ુ ુ

સમ વો.

07

બ RISC તથા CISC મા ંકોણ ચઢ યા ંછ ત સરખમણી કર ન સમ વોુ ે ે ે . 07

અથવા

. 3 અ દા દા ુ ુ સ શન ફોમટ ( યથી ણ એ સ ોૂ ે )નીચના ગણતીક ે

કથન માટ સમ વો તથા સરખાવો: A=(B*C)+(D/E).

07

બ ટક ઓગનાઈ ડ સીપી નુો ઉપયોગ આ િતસહ સમ વો. 07

. 4 અ સામા ય માઇ ો ો ામડ કં ોલ ણા લના દરક ભાગન દોર ન સમ વોે ે . 07

બ માઇ ો ો ામડ કં ોલ બધંારણ ંહાડવર દોરુ ે તથા સમ વી બતાવો. 07

અથવા

. 4 અ એકથી વધાર ફકશનલ િનટો ધરાવં ુ ંસમાતંર બધંારણ આ િતસહ ુ

સમ વો.

07

બ ચાર સગમટ ધરાવતી ે સ શન પાઈપ-લાઈન, લો ચાટ ારા

સમ વો.

07

. 5 અ પાઈપ-લાઈન કો ટગમા ં પીડુ -અપ ંછુ ે? S

( પીડ-અપ) = k (સ મટની સં યાે ) સા છ ત બતાવોુ ે ે .

07

બ પાઈપ-લાઈન ક લી સ ઉપર ંક ન ધ લખોુ . 07

અથવા

. 5 અ સ ોનાઉઝ તથા એસ ોનાઉઝ ડટા ાસંફરના તફાવતો જણાવો. 07

બ કશ મમર મા ંે �રાઇટ �ુ તથા �રાઇટ બૅક� ંછુ ે 07

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