A Precision Low-Power Mismatch-Compensated Sample-and-Hold Circuit for Biomedical

Applications S.L. Mah#1, P.K. Chan*2, Shiv Kumar Mishra#3

School of EEE, Nanyang Technological University, Singapore 1 mahs0001@ntu.edu.sg,1 shiv0002@ntu.edu.sg,1 epkchan@ntu.edu.sg

Abstract— This paper presents a new micro-power precision sample-and-hold (S/H) circuit for biomedical applications. In conjunction of low-power op-amp circuit design, the switched-capacitor capacitive-reset gain circuit with capacitor-mismatch compensation technique has been used. With this combination, the S/H has features of insensitive to capacitor mismatch, offset, and finite open-loop gain of op-amp whilst offering rail-to-rail characteristic. Operating at 1.8 V supply, the S/H circuit consumes 6.69 µA for low power design. At a sampling frequency of 128 kHz and in response to 1-Vpp and 1-kHz sinusoidal input, the S/H circuit has achieved less than 0.081 mV of hold-pedestal , –75.96 dB of total harmonic distortion (equivalent to 12.62 bits of ENOB) and . / of Figure of Merit (FOM). Keywords— Sample-and-Hold Circuits, Switched-Capacitor Circuits, Capacitor Mismatch.

I. INTRODUCTION Sample-and-hold (S/H) circuit, an important building block

in analog-to-digital converter, is used to sample an analog signal and to store its value for signal conversion and digital signal processing. In biomedical application, power consumption is a crucial design factor for implant electronics or portable devices. Hence, the S/H circuit employed in biomedical devices should dissipate as minimum power as possible whilst yet offering reasonable good accuracy for bio-signal processing.

This work focuses on the switched-capacitor (SC) capacitive-reset gain circuit structure [1] because it has advantages of insensitive to op-amp’s input offset, reduced op-amp’s 1/f noise, finite gain compensation, low power due to reduced slew rate through built-in sample-and-hold operation. For the S/H application, the closed loop gain of the amplifier can be made unity through defining the ratio of the input and feedback capacitor to be one. However, it suffers from capacitor mismatch problem and hence, the maximum accuracy is limited to 10 bit on the basis of layout limitation. To extend the accuracy of S/H circuit, the capacitor interchange technique [2] for mismatch compensation is explored. To achieve high precision and low power objectives, the SC capacitive reset unity-gain structure as well as low-power op-amp design incorporating the capacitor mismatch compensation is proposed in this paper.

II. PROPOSED S/H CIRCUIT The basic idea of this circuit is, by appropriate switching of

feedback capacitor, and input capacitor, , mismatch effect can be cancelled and the output is an exact replica of input sampled. This technique has been used in a ratio-independent ADC circuit [2] or a two-capacitor DAC circuit [3]. Fig. 1 shows the proposed S/H circuit using capacitive-reset gain circuit with capacitor-mismatch compensation.

Fig. 1 Capacitive-reset gain circuit with capacitor-mismatch compensation

SW1, SW2, SW9 and SW13 were realized using CMOS transmission gate with dummy to reduce the signal dependent charge injection errors. Switches connected to high impedance node, namely SW5-SW8, were implemented using dummy switches. The rest of the switches were realized using NMOS single switches as the charge injection errors caused by these switches were insignificant. These were verified by simulation.

A. Operation of the Proposed S/H Circuit The S/H circuit operation involves 4 phases, namely reset

phase ( ), sampling phase ( ), charge transfer phase ( ), mismatch-compensation phase ( ) and hold phase ( ). (Note: For simplicity, the notation for V(n) and Q(n) means voltage and charge stored in a capacitor at phase n respectively, where n=0,1, 2, 3, 4.

1) Reset Phase ( ): The reset clock, , is required only one time in the initial phase of non-overlapping clocks to reset

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the capacitors for short duration prior to the S/H circuit operation. It discharges all the capacitors and related nodes to analog ground, thus defining the biasing points of circuit.

2) Sample Phase ( ): The input is applied to the circuit as

depicted in Fig. 2(b). The signal is sampled to C1 on the falling edge of clock signal. The capacitor C3 holds the output voltage value during this phase. is the offset voltage at the non-inverting input of the op-amp.

(1)= (1) (1) (1)= (2) (1) = (1) (3)

3) Charge Transfer Phase ( ): Charge transfer takes place between the input capacitor C1 and output feedback capacitor C2 during this phase.

(2)= (4) (2)= (2) (5) (2) = (2) (6) By charge conservation at the node of inverting input of op-amp, we have ∆ = ∆ (7) (2) (1) = (2) (1) (8) Substituting (1), (2), (4) and (5) into (8), we get (1)= (3) (9) (2) = (2)= (1) (10)

(9) shows that the hold capacitor C3 updates the hold value defined by the gain function C1/C2.

-+

-+

Fig. 2 (a) Reset Phase ( ) (b) Sample Phase ( ) (c) Charge Transfer Phase (d) Mismatch-Compensation Phase

4) Mismatch-Compensation Phase ( ): The cancellation of mismatch error takes place during the clock phase . As depicted in Fig. 2(d), the position of two capacitors C1 and C2 are swapped. The final output in is obtained as follows: (3) = (3) = (2) = (1) (11) (3) = (1) (12)

5) Hold Phase ( ): This is the last phase that the capacitor C1 in feedback path performs the hold function whereas the output is coupled to the next stage at the clock signal as depicted in Fig. 3. Finally, we get

(4) = (3) = (1) (13)

Fig. 3 Hold Phase

From (13), it can be seen that the final output is independent of the capacitor mismatch.

B. Low-Power Cascode-Compensated Op-Amp

Fig. 4 Op-Amp used in the proposed S/H circuit

Fig. 4 is a CMOS two-stage op-amp that combines the front-end current mirror cascode compensation stage (P1-P3, N1-N4) and the output push-pull stage (P6-P7, N6-N7).. A wide-swing cascode mirror (N1-N4) serves as an active load and frequency compensation for obtaining good power-bandwidth efficiency. Push-pull stage provides rail-to-rail output swing while improving the load driving ability. P1-P2 operate in weak inversion region. This can be estimated by

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inversion coefficient, = [4] where 0.1 for deep weak inversion.

III. SIMULATION RESULTS AND DISCUSSIONS The S/H circuit was designed using GLOBALFOUNDRIES

0.18 µm CMOS process technology and simulated using realistic BSIM3 model parameters. The S/H circuit samples at 125 kHz. At an analog ground of 0.8 V, the circuit was applied with a 1-Vpp and 1-kHz sinusoidal input. The size of C1, C2 and C3 were 1 pF, 1 pF and 20 pF, respectively. The op-amp performance is summarized in Table I. The effect of mismatch-compensation method is verified and the results are shown in Table II. Performance parameters of the proposed S/H circuit such as hold pedestal and total harmonic distortion (THD) were also examined. Finally, the performance metrics were compared with previous reported works in Table III.

A. Performance of Op-Amp At a supply voltage of 1.8V, the simulated performance of

the op-amp is summarised in Table I.

TABLE I PERFORMANCE PARAMETERS OF THE OP-AMP

Parameter Value Open Loop Gain 93.64dB

Phase Margin 59.36 Unity Gain Bandwidth 2.53 MHz

30.5 pF Power Dissipation @ 1.8 V power supply 12.04 μW

Total Current Consumption 6.69 μA A unity-gain bandwidth of 2.53 MHz is adequate for bio-

signal conditioning. It can be seen that deployment of weak-inversion design technique combined with cascode frequency compensation scheme results in a total current consumption of 6.69 μA, contributing power consumption of only 12.04 μW.

B. Capacitor-Mismatch Compensation The use of mismatch compensation method aims to

eliminate the error caused by mismatch between C and C . Thus, simulation was done to show how effective this method is by intentionally introducing capacitor mismatch. Outputs were recorded at a few holding points and compared with the corresponding sampled inputs. It can be seen from Table II shows that the changes in output are in the order of 0.0001% which is insignificant. Hence, this confirms that the mismatch compensation method is effective.

C. Hold Pedestal Hold pedestal or hold error is an error that occurs every

time a circuit goes from sample to hold mode. There is always a small error in the voltage being held, making the held voltage to be different from the input voltage at the time of

sampling [1]. It is desirable to have this error to be as small as possible. In response to 1-Vpp and 1 kHz sinusoidal input, the hold pedestals at the same points used in section B were examined. This work has achieved the hold pedestal less than 0.081 mV.

Fig. 5 Measurement of Hold Error

TABLE II COMPARISON OF FOR NO MISMATCH AND 2% MISMATCH BETWEEN AND

(V) , (V) No Mismatch = =

, (V) 2% Mismatch = = .

% Difference

0.906139 0.906068 0.906066 -0.0002% 0.930739 0.930666 0.930664 -0.0002% 1.241131 1.241063 1.241062 -0.0001% 1.258709 1.258644 1.258642 -0.0002% 1.399742 1.399709 1.399707 -0.0002% 1.399927 1.399896 1.399894 -0.0002% 1.263904 1.263904 1.263902 -0.0002% 1.246586 1.246588 1.246587 -0.0001% 0.913653 0.913655 0.913652 -0.0002% 0.889036 0.889037 0.889035 -0.0002% 0.654032 0.654021 0.654016 -0.0004% 0.632905 0.632891 0.632887 -0.0004% 0.407224 0.407182 0.407179 -0.0003% 0.403653 0.403609 0.403606 -0.0003% 0.634713 0.634647 0.634643 -0.0005% 0.655894 0.655829 0.655824 -0.0005% 0.866577 0.866507 0.866503 -0.0004% 0.891171 0.891101 0.891097 -0.0004%

D. Total Harmonic Distortion Total harmonic distortion is defined as the square root of

the ratio of the sum of all of the second and higher harmonics to the magnitude of the first or fundamental harmonic. In S/H context, THD reflects the held values as well as the tracking component of the waveform where a substantial source of non-linearity exists [7]. Fig. 6 shows a Discrete Fourier Transform of V in response with 1Vpp of input at 1 kHz. THD can be calculated as follows:

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= … % (14)

Different input frequencies were applied and the corresponding THD values were calculated. Fig. 7 shows the THD in response to different input frequencies. At 1 kHz frequency, the THD is -75.96dB. This is translated to 12.62 ENOB. For -60dB reference point, the maximum frequency is about 4.5 kHz, which is adequate for many biomedical signal-processing or conditioning.

Fig. 6 DFT plot of in response to 1-Vpp 1-kHz input frequency

Fig. 7 THD (dB) of in response to 1-Vpp input at different frequencies

E. Figure of Merit (FOM)

In order to normalize the power efficiency [6], this paper proposes to use the total current consumption instead of the total power consumption. It factors out the influence of the different supply voltages for power efficiency. The FOM is defined as follows: FOM = T ENOBTHD = P/VDDENOBTHD μA/MHz (15)

where P is power consumption, is supply voltage and is sampling frequency. The lower the FOM, the better the power efficiency of a S/H is. This work has achieved a FOM of 8.30 10 µA/MHz , which is comparable with other reported works as shown in Table III.

IV. CONCLUSION Though mismatch compensation method creates a latency

of 1 clock period between input and output when compared to that of conventional circuit, the proposed S/H circuit is almost independent on the mismatch of capacitor pair. Besides, by choosing suitable switches and appropriate value of holding capacitor, the hold pedestal can actually be reduced to very small value. Since this work is designed for biomedical signals having frequencies of few kHz, THD performance is good even in single-ended circuit architecture. The proposed circuit techniques permit the S/H circuit to achieve low power, high precision as well as significant FOM value when compared with the reported prior-art works.

REFERENCES

[1] D. Johns and K. W. Martin, Analog Integrated Circuit Design. John Wiley & Sons, 1997, pp. 706. [2] W. Li, M. J. Chin, P.R. Gray and R. Castello, “A ratio-independent algorithmic analog-to-digital conversion technique”, IEEE J. of Solid-State Circuits, vol. sc-19, no. 6, pp. 828-836, Dec. 1984. [3] X. Liu, X. Zheng and H. Liu, “Voltage averaging technique for improving the resolution of two-capacitor DAC”, Asia Pacific Conference on Circuit and Systems (APCCAS), pp. 1529-pp. 1532, Dec. 2008. [4] D. Foty, M. Bucher M and D. Binkley, "Re-interpreting the MOS transistor via the inversion coefficient and the continuum of gms/Id", 9th International Conference on Electronics, Circuits and Systems, 2002. [5] A. Boni, A. Pierazzi and C. Morandi, "A 10-b 185-MS/s track-and-hold in 0.35-μm CMOS," IEEE Journal of Solid-State Circuits, vol. 36, pp. 195-203, 2001. [6] A. Baschirotto, "A low-voltage sample-and-hold circuit in standard CMOS technology operating at 40 ms/s," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, pp. 394-399, 2001. [7] T. S. Lee, C. C. Lu and Z. T. Zhan, "A 250MHz 11Bit 20mW CMOS Low-Hold-Pedestal Fully Differential Track-and-Hold Circuit", International Symposium on VLSI Design, Automation and Test, Hsinchu, 2006. [8] H. H. Ou, B. D. Liu and S. J. Chang, "A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture," IEICE Transaction on Electronics, vol. E91-C No. 9, pp. 1480-1487, 2008.

TABLE III COMPARISON OF THIS WORK WITH PREVIOUSLY REPORTED WORKS

Parameter Boni [5] Baschirotto [6] Lee [7] *Hsin-Hung [8] *This work CMOS Technology 0.35 μm 0.5 μm 0.35 μm 0.13 μm 0.18 μm

Sampling Rate 185MHz 40 MHz 250 MHz 250 MHz 128 kHz Full-scale Input Range 1 Vpp 0.6 Vpp 1.8 Vpp 0.8 Vpp 1 Vpp

Hold Pedestal 5 1 0.39 0.081 THD -63dB @45MHz -50dB@2MHz -69dB@85 MHz -67.3dB@25MHz -75.96dB@ 1 kHz

Supply Voltage (V) 3.3 1.2 3 0.8 1.8 Power Consumption 70mW 1.2 mW 20 mW 3.5 mW 12.04 W

Total Current Consumption (mA) 21.2 1.00 6.67 4.38 6.69 10 10.46 8.3 11.46 11.18 12.62

FOM (µA/MHz) 1.12 10 9.77 10 1.30 10 8.54 10 8.30 10 * This work and reference provide simulation results only. Other works provide experimental results.

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