ABHISHEK KRISHNA +1 203-690-9547 | www.linkedin.com/in/abhishekkrishn | abkrishn@my.bridgeport.edu

● Seeking an internship/co-op/full-time opportunity in RTL/IC/Hardware Design, ASIC, SoC or Verification domain (summer 2016) EDUCATION

MS in Electrical Engineering University of Bridgeport, CT, USA GPA: 3.853 Aug’16 RELEVANT COURSES: ● Digital VLSI ● Micro/Nano electronic fabrication ● Low power VLSI circuit design ● Advanced digital systems ● VLSI testing ● Introduction to nanotechnology ● Radio Frequency VLSI ● Python Programming ● Advanced Sensor Technology ● Data Computer Communication ● Field Programmable Gate Array TECHNICAL SKILLS (1 year 3 months academic experience)

● Solid Knowledge: - FSM, FPGA, DFT, ASIC, VLSI, RF, SoC, RTL, RISC & CISC, FIFO & LIFO, UVM, OVM, ATPG, MBIST, LBIST, PRPG, MISR, LVS, PAL, PLC, MIPS , Testing, Memories, Scan chain, IP protocols, Hardware Design, Debugging, Netlist extraction, Synthesis, Fabrication, Digital Logic Design, Lithography process, Logic shut down techniques, Layout, Schematic, Timing analysis, Microcontroller ● Languages: - Verilog, VHDL, System Verilog, Python, C, C++ ● Tools Used: - Synopsys, Xilinx ISE and Vivado, ModelSim, Mentor Graphics, Calibre, Quartus II, Comsol, Qsim, NCsim, Irsim, OPNET, VLSI EDA tool, Cadence, CAD PSPICE, QCADesigner. ● FPGA Boards: - ALTERA cyclone II DE2, Spartan 6, Xilinx (Virtex 4 and Virtex 6) ● Operating Systems: - Linux, Windows EXPERIENCE

● Graduate Assistant and Teaching Associate for Low power VLSI ckt design at EE department UB Jan’16- present Assisted professor in research, taking Lab classes, grading the class assignments and exams, Clarified doubts on course, helped student to understand concepts and mentored students on their course projects

● Assistant Electrical Engineer at Yeduguri Infra Projects Pvt. Ltd Jul’13-Apr ‘14 Assisted project manager with electrical designs and implementations

● Technical Intern at Electronics Corporation of India Ltd (ECIL), Bangalore Jan’13-Jun’13 Worked on a new design of Microcontroller (8051) based maximum Solar Power tracking and Application

ACADEMIC PROJECTS

[1] Low Cost, Portable Non-Invasive Blood Sugar Detection (Awarded Third Prize in ASEE conference 2016) ● Research focuses on developing a complete lab-on-a-chip system for the sample (Saliva) collection, preparation and transportation so

that the glucose level in the biological sample can be sensed and read out for LED display. ● Lab-on-a-chip system is designed and simulated COMSOL Feb’16 [2] Design and Implementation of Dynamically Configured Multi-port Cache Memory employing new DMP Technique ● 6*64-bit decoder, 32*64-bit SRAM and circuit for DMP algorithm is constructed to make a multi port Cache memory which can

process faster than a conventional Cache memory using minimum power. ● Construction, timing analysis, DRC and LVS of schematic and layout VHDL, Mentor graphics Mar’15 LCD Graphic Controller ● Implemented, designed and verified the controller design as found in LPC24XX data sheet. This graphics controller is both an AHB

master and an AHB slave. ● Implementation and verification of LCD Timing Controller, LCD panel clock generator, pixel serializer and RAM palette modules were

my major contribution to the project. System Verilog, Synopsys VCS Sep’15 NIOS II Processor ● Implemented a subset of NIOS II instruction set architecture that executes the dot product benchmark program using Synopsys VCS

and displayed working simulations of NIOS II design for two given vectors. ● Implemented multi-cycle instruction execution stages Verilog Nov’15 32-bit LFSR MIPS architecture ● 32-bit data is entered and Random test pattern number is generated using Linear Feedback Shift Register. ● Timing analysis is done by coding as well as construction of schematic and layout Verilog, Mentor Graphics Jun’15 Complex Vending Machine ●FSM is constructed as per the requirements of the machine operation ● Implemented and observed the desired output. Synthesized and generated the hardware FPGA Board, VHDL Mar’16 16-bit ALU with Carry look ahead Architecture ● Design performed addition, subtraction, multiplication, division, parallel in parallel out, Serial in serial out and comparator ● LUT mapping with 2 input combinational output techniques is implemented. Xilinx 4000 CLB, VHDL Apr’16 AWARDS and CERTIFICATIONS

● Academic Accomplishment Award ‘Valedictorian’ of Electrical Department (GRADUATE) May’16 ● Introduction to Computer Science and Programming Using Python Aug’15- Nov’15 Massachusetts Institute of Technology (MIT), Cambridge, MA, US ● CCE-PROFICIENCE PROGRAMME (Course continuing Education) on Advanced Sensor Technology Aug’13 – Jan’14 Indian Institute of Science (IISc), Bangalore, India [1] & [2] Presented in ASEE-NE CONFERENCE